IBIS Macromodel Task Group Meeting date: 21 August 2018 Members (asterisk for those attending): ANSYS: Dan Dvorscak * Curtis Clark Cadence Design Systems: Ambrish Varma Brad Brim Kumar Keshavan Ken Willis eASIC: David Banas GlobalFoundries: Steve Parker IBM Luis Armenta Trevor Timpane Intel: * Michael Mirmak Keysight Technologies: * Fangyi Rao * Radek Biernacki * Ming Yan * Stephen Slater Mentor, A Siemens Business: John Angulo * Arpad Muranyi Micron Technology: Randy Wolff * Justin Butterfield SiSoft: * Walter Katz * Mike LaBonte SPISim: Wei-hsing Huang Synopsys: Rita Horner Kevin Li Teraspeed Consulting Group: Scott McMorrow Teraspeed Labs: * Bob Ross The meeting was led by Arpad Muranyi. Curtis Clark took the minutes. -------------------------------------------------------------------------------- Opens: - None. ------------- Review of ARs: - Randy to investigate if/why/how a clock waveform input might be used. - In progress. - Michael M. to investigate if/why/how a clock waveform input might be used. - In progress. -------------------------- Call for patent disclosure: - None. ------------------------- Review of Meeting Minutes: Arpad asked for any comments or corrections to the minutes of the August 14 meeting. Michael M. moved to approve the minutes. Walter seconded the motion. There were no objections. ------------- New Discussion: Arpad noted that in future ATM agenda emails he would combing items 6 and 7 into a single "AMI Improvements" topic. Walter agreed that this was a good idea. AMI Improvements: Arpad asked if we should continue the previous meeting's conversation about Fangyi's presentation. He noted there had been a suggestion to take a straw poll on which items should definitely be addressed with a BIRD. Walter proposed that we start by creating an email list of problems on-the-fly with group input. The resulting list of possible issues to be addressed was sent to the ATM group shortly after the meeting (email titled "IBIS-ATM strawmen poll about what needs to be addressed"). The email asked people to review the list, choose the topics they felt must be addressed, and reply to Bob Ross no later than two hours before the next meeting on August 28th. Highlights from the discussions of topics on the list: Rise/Fall asymmetry - Arpad noted that Ambrish had said the EDA tool could take care of this without changes in the spec. Walter noted that he agreed with Ambrish. Walter said one possible solution was to document a different flow. Mix of single ended and differential signals - Fangyi suggested this item. Arpad noted, for example, DQ and DQS having to be simulated together. Walter said he considered this topic the same as clock forwarding. Fangyi said this topic was about defining the waveform passed to GetWave(). Arpad noted that Fangyi had previously suggested the model would need to know if it were in read or write mode. Walter said if a model were for a controller or a model were for a DRAM then the direction would be understood. For example, if the model were for the DRAM, then Rx would be on a write cycle and Tx on a read cycle. Fangyi agreed that if models were for the DRAM or for the controller then the direction would be understood. DQ Nibbles - Walter noted that these would be what Fangyi had called Component models. For example, a particular memory controller might support different skews between each DQ and the DQS. Fangyi agreed skew was one problem for a Component based model, and noted another was a Vref shared across a backplane. Power Aware SSO effects on AMI modeling - Michael M. asked if a solution for the rise/fall might also address this, given the non-LTI issues with both. Fangyi said this was not likely. He noted that rise/fall asymmetry is a non-linear effect, and power rail noise is time varying effect. Walter agreed the answer was no. He said there are two SSO effects, crosstalk and power modulation. AMI can handle the former, and the latter likely needs to be handled using spectral density information obtained from a power rail simulation. Arpad asked if we could correctly model these effects with an independent distribution function when in fact the modulation of the power rail depends on what devices are reading/writing at a given time. Fangyi agreed that the power fluctuations are correlated to the bit pattern. Walter said it was a good question, and it gets complicated, but in his experience chip vendors could characterize their power rail modulation by measurement or simulation and build the info into their eye margin values. Stephen said the point of the straw poll was to work out what people agreed upon as important issues. These could be considered the low hanging fruit, while things that were more contentious could be discussed later. Arpad said he wanted more from the straw poll. He wanted to know whether a company that wanted all the issues addressed would be happy if only a subset were handled. Is it an all or nothing proposition? How far can we go if we can only agree on a few of the items and not all of them? At Stephen's request, Walter listed the items SiSoft considered must-haves (see email). Walter also noted that he could explain why he didn't think a clock input to the .dll was necessary, but he said he preferred to wait for Randy and MM to explain how they might use it (in progress ARs). Stephen proposed that companies might review the list and send their straw poll votes to an independent party (Bob Ross was nominated and accepted) to tabulate the results. - Mike L.: Motion to adjourn. - Walter: Second. - Arpad: Thank you all for joining. AR: Arpad to send the straw poll email to the ATM. ------------- Next meeting: 28 August 2018 12:00pm PT ------------- IBIS Interconnect SPICE Wish List: 1) Simulator directives